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fn6690 rev 1.00 page 1 of 19 sep 26, 2008 fn6690 rev 1.00 sep 26, 2008 isl12008 i 2 c real time clock with battery backup low power rtc with battery reseal? function datasheet the isl12008 device is a low power real time clock/calendar that is pin compatible and f unctionally equivalent to the st m41t00s and maxim ds13 40 with timing and crystal compensation. the device addit ionally provides power-fail indicator, software alarm and intelligent battery backup. the oscillator uses an external , low-cost 32.768khz crystal. the real time clock tracks time w ith separate registers for hours, minutes, and seconds. the device has calendar registers for date, month, y ear and day of the week. the calendar is accurate through 2 099, with automatic leap year correction. pinout isl12008 (8 ld soic) top view features ? pin compatible to st m41t00s and maxim ds1340 ? functionality equivalent to st m41t00 s and maxim ds1340 ? real time clock/calendar - tracks time in hours, minutes, seconds and sub-seconds - day of the week, day, month, and year ? 512hz frequency outputs for on-chip crystal compensation ? software alarm - settable to the second, minute, hour, day of the week, day, or month ? automatic low-drop batter y switch for longest backup life ? power failure detection ? battery reseal ? for long shelf life ?i 2 c bus? - 400khz data transfer rate ? 800na battery supply current ? small package option - 8 ld soic ? pb-free (rohs compliant) applications ? utility meters ? hvac equipment ? audio/video components ? set-top box/television ? modems ? network routers, hubs, switches, bridges ? cellular infrastructure equipment ? fixed broadband wireless equipment ? pagers/pda ? pos equipment ? test meters/fixtures ? office automation (copiers, fax) ? home appliances ? computer products ? other industrial/medical/automotive . ordering information part number (note) part marking v dd range (v) temp. range (c) package (pb-free) pkg. dwg. # ISL12008IB8Z 12008 ibz 2.7 to 5.5 -40 to +85 8 ld soic m8.15 ISL12008IB8Z-t* 12008 ibz 2.7 to 5.5 -40 to +85 8 ld soic m8.15 *please refer to tb347 for det ails on reel specifications. note: these intersil pb-free pl astic packaged products employ sp ecial pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb -free peak reflow temperatures that meet or exceed the pb-free requirement s of ipc/jedec j std-020. 1 2 3 4 8 7 x1 x2 v bat v dd ft/out scl sda gnd 5 6
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 2 of 19 sep 26, 2008 block diagram i 2 c interface rtc control logic frequency out rtc divider sda buffer crystal oscillator por switch scl buffer sda scl x1 x2 v dd v bat ft/out internal supply v trip seconds minutes hours day of week date month year control registers pin number symbol description 1 x1 the x1 pin is the input of an inverting amplifier and is int ended to be connected to one pin of an external 32.768khz quart z crystal. x1 can also be driven directly from a 32.768khz source . 2 x2 the x2 pin is the output of an inverting amplifier and is in tended to be connected to one pin of an external 32.768khz quar tz crystal. 3v bat this input provides a backup su pply voltage to the device. v bat supplies power to the device in the event that the v dd supply fails. this pin should be tied to ground if not used. 4 gnd ground 5 sda serial data (sda) is a bidir ectional pin used to transfer s erial data into and out of the device. it has an open drain out put and may be wire ored with other open drain or open collector outpu ts. 6 scl the serial clock (scl) inpu t is used to clock all serial da ta into and out of the device. 7 ft/out 512hz frequency output or digital output pin. the functi on is set via the configuration register. this pin is open drai n and requires an external pull-up resistor. 8v dd power supply
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 3 of 19 sep 26, 2008 absolute maximum ratings thermal information voltage on v dd , v bat , scl, sda, and ft/out pins (respect to gnd). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 6.5v voltage on x1 and x2 pins (respect to gnd) v dd mode. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd + 0.5 v bat mode . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v bat + 0.5 thermal resistance (typical, note 1) . . . . . . . . . . . . . . . ? ja (c/w) 8 lead soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 1. ? ja is measured with the componen t mounted on a high effective t hermal conductivity te st board in free air . see tech brief tb37 9 for details. dc operating characteristics C rtc temperature = -40c to +85c. r ecommended operating conditions, unless otherwise specified. symbol parameter conditions min (note 8) typ (note 5) max (note 8) units notes v dd main power supply 2.7 5.5 v v bat battery supply voltage 1.8 5.5 v i dd1 supply current v dd = 5v 2.8 6 a 2, 3 v dd = 3v 1.6 4 a i dd2 supply current with i 2 c active v dd = 5v 40 120 a 2, 3 i dd3 supply current (low power mode) v dd = 5v, lpmode = 1 2.3 5 a 2 i bat battery supply current v bat = 3v, +25c 800 950 na 2 i li input leakage current on scl -1 0.1 +1 a i lo i/o leakage current on sda -1 0.1 +1 a v trip v bat mode threshold 2.3 2.6 2.9 v v triphys v trip hysteresis 36 mv 6 v bathys v bat hysteresis 53 mv 6 ft/out v ol output low voltage v dd = 5v i ol = 3ma 0.02 0.4 v v dd = 2.7v i ol = 1ma 0.02 0.4 v power-down timing temperature = -40c to +85c. recommended operating conditions unless otherwise specified. symbol parameter conditions min (note 8) typ (note 5) max (note 8) units notes v dd sr- v dd negative slewrate 5v/ms 4 serial interface specifications recommended operating conditio ns. unless otherwise specified. symbol parameter test conditions min (note 8) typ (note 5) max (note 8) units notes serial interface specs v il sda and scl input buffer low voltage -0.3 0.3 x v dd v v ih sda and scl input buffer high voltage 0.7 x v dd v dd + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v dd v 6, 7 v ol sda output buffer low voltage, sinking 3ma 0 0.02 0.4 v cpin sda and scl pin capacitance t a = +25c, f = 1mhz, v dd = 5v, v in = 0v, v out = 0v 10 pf 6, 7
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 4 of 19 sep 26, 2008 f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge cross ing 30% of v dd , until sda exits the 30% to 70% of v dd window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v dd during a stop condition, to sda crossing 70% of v dd during the following start condition. 1300 ns t low clock low time measured at the 30% of v dd crossing. 1300 ns t high clock high time measured at the 70% of v dd crossing. 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of v dd . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v dd to scl falling edge crossing 70% of v dd . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v dd window, to scl rising edge crossing 30% of v dd. 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v dd to sda entering the 30% to 70% of v dd window. 20 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v dd , to sda rising edge crossing 30% of v dd . 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v dd . 600 ns t dh output data hold time from scl falling edge crossing 30% of v dd , until sda enters the 30% to 70% of v dd window. 0ns t r sda and scl rise time from 30% to 70% of v dd 20 + 0.1 x cb 300 ns 6, 7 t f sda and scl fall time from 70% to 30% of v dd 20 + 0.1 x cb 300 ns 6, 7 cb capacitive loading of sda or scl total on-chip and off-chip 10 4 00 pf 6, 7 rpu sda and scl bus pull-up resistor off-chip maximum is determin ed by t r and t f . for cb = 400pf, max is about 2k ? to~2.5k ? . for cb = 40pf, max is about 15k ?? to ~20k ?? 1k ? 6, 7 notes: 2. ft/out inactive. 3. lpmode = 0 (default). 4. in order to ensure proper timekeeping, the v dd sr- specification must be followed. 5. typical values are for t = +25c and 3.3v supply voltage. 6. limits should be considered ty pical and are not production te sted. 7. these are i 2 c specific parameters and are not tested, however, they are use d to set conditions for testing devices to validat e specificati on. 8. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. temperature limits established b y characterization and are not production tested. serial interface specifications recommended operating conditio ns. unless otherwise specified. (continued) symbol parameter test conditions min (note 8) typ (note 5) max (note 8) units notes
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 5 of 19 sep 26, 2008 sda vs scl timing symbol table t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 6 of 19 sep 26, 2008 general description the isl12008 device is a low power real time clock with timing and crystal compensation, clock/calendar, power fail indicator, software alarm, and intelligent battery backup switching. the oscillator uses an external , low-cost 32.768khz crystal. the real time clock tracks time w ith separate registers for hours, minutes, seconds, and su b-seconds. the device has calendar registers for date, mont h, year and day of the week. the calendar is accurate thro ugh 2099, with automatic leap year correction. the isl12008's powerful a larm can be set to any clock/calendar value for a match . for example, every minute, every tuesday or at 5:23 am on march 21. the alarm status is available by checking the status register. the device also offers a backup power input pin. this v bat pin allows the device to be backed up by battery or super capacitor with automatic switchover from v dd to v bat . the entire isl12008 device is fully operationa l from 2.7v to 5.5v and the clock/calendar portion of the de vice remains fully operational down to 1.8v in battery mode. pin descriptions x1, x2 the x1 and x2 pins are the input and output, respectively, of a n inverting amplifier. an external 32.768khz quartz crystal is us ed with the isl12008 to supply a timebase for the real time clock. internal compensation ci rcuitry provides high accuracy over the operating temperature range from -40c to +85c. this oscillator compensation network can be used to calibrate the crystal timing accuracy over- temperature either during typical performance curves temperature is +25c, unl ess otherwise specified. figure 1. i bat vs v bat figure 2. i bat vs temperature at v bat = 3v figure 3. i dd1 vs temperature figure 4. i dd1 vs v dd with lpmode on and off 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v bat (v) i bat (a) 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 -40-200 20406080 temperature (c) i bat (a) 1.0 1.5 2.0 2.5 3.0 3.5 -40-200 20406080 temperature (c) i dd (a) v dd = 3.3v v dd = 5v 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.82.32.83.33.84.34.85.3 v dd (v) i cc (a) lp mode off lp mode on figure 5. standard output load for testing the device with v dd = 5.0v sda and ft/out 1533 ? 100pf 5.0v for v ol = 0.4v and i ol = 3ma equivalent ac output load circui t for v dd = 5v
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 7 of 19 sep 26, 2008 manufacturing or with an exte rnal temperature sensor and microcontroller for active c ompensation (see figure 6). v bat this input provides a backup su pply voltage to the device. v bat supplies power to the devic e in the event that the v dd supply fails. this pin can be connected to a battery, a super capacitor or tied to g round if not used. ft/out (512hz frequency output/logic output) this dual function pin can be used as a 512hz frequency output pin for on-chip crystal c ompensation or a simple digital output control via i 2 c. the ft/out mode is selected via the out and ft control bits of the co ntrol/status register (address 07h). this pin is an open drain output requires the use of a pull-up resistor. serial clock (scl) the scl input is used to clock all serial data into and out of the device. the input buffer on this pin is always active (not gate d). it is disabled when the backup power supply on the v bat pin is activated to minimize power consumption. serial data (sda) sda is a bidirectional pin used to transfer data into and out o f the device. it has an open dr ain output and may be ored with other open drain or open collec tor outputs. the input buffer is always active (not gated) in normal mode. an open drain output requires th e use of a pull-up resistor. th e output circuitry cont rols the fall time of the output signal wi th the use of a slope controlled pull-down. the circuit is designe d for 400khz i 2 c bus speeds. it is disabled when the backup power supply on the vba t pin is activated. v dd , gnd chip power supply and ground pi ns. the device will operate with a power supply from 2.7v to 5.5vdc. a 0.1f decoupling capacitor is recommended on the v dd pin to ground. functional description power control operation the power control circuit accepts a v dd and a v bat input. many types of batteries can be used with intersil rtc products. for example, 3.0v or 3.6v lithium batteries are appropriate, and battery sizes are available that can power the isl12008 for up to 10 years. anot her option is to use a super capacitor for applications where v dd is interrupted for up to a month. see application se ction on page 16 for more information. normal mode (v dd ) to battery backup mode (v bat ) to transition from the v dd to v bat mode, both of the following conditions must be met: condition 1: v dd < v bat - v bathys where v bathys ? 50mv condition 2: v dd < v trip where v trip ? 2.6v battery backup mode (v bat ) to normal mode (v dd ) the isl12008 device wi ll switch from the v bat to v dd mode when one of the following conditions occurs: condition 1: v dd > v bat + v bathys where v bathys ?? 50mv condition 2: v dd > v trip + v triphys where v triphys ? 30mv these power control situations a re illustrated in figures 7 and 8. figure 6. recommended crystal connection x1 x2 v bat - v bathys v bat v bat + v bathys battery backup mode v dd v trip 2.6v 1.8v figure 7. battery switchover when v bat < v trip figure 8. battery switchover when v bat > v trip v trip v bat v trip + v triphys battery backup mode v dd v trip 3.0v 2.6v
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 8 of 19 sep 26, 2008 the i 2 c bus is deactivated in battery backup mode to provide lower power. aside from this, all rtc functions are operational during battery backup mode. except for scl and sda, all the inputs and outputs of the isl12008 are active during battery backup mode unless disabled via the control register. power failure detection the isl12008 provides a real time clock failure bit (rtcf, address 0bh) to detect total power failure. it allows users to determine if the device has powe red up after having lost all power to the device (both v dd and v bat ). low power mode the normal power switching of the isl12008 is designed to switch into battery ba ckup mode only if the v dd power is lost. this will ensure that the device can accept a wide range of backup voltages from many types of sources while reliably switching into backup mode. another mode, called low power mode, is available to allow direct switching from v dd to v bat without requiring v dd to drop below v trip . since the additional monitoring of v dd vs v trip is no longer needed, that circuitry is shut down and less power is used while operating from v dd . power savings are typically 600na at v dd = 5v. low power mode is act ivated via the lpmode bit (address 08h, bit 5) in the control and status registers. low power mode is useful in systems where v dd is normally higher than v bat at all times. the dev ice will swit ch from v dd to v bat when v dd drops below v bat , with about 50mv of hysteresis to prevent any switchback of v dd after switchover. in a system with a v dd = 5v and backup lithium battery of v bat = 3v, low power mode can b e used. however, it is not recommended to use low power mode in a system with v dd = 3.3v 10%, v bat ? 3.0v, and when there is a finite i-r voltage drop in the v dd line. interseal? and reseal? battery saver the isl12008 has the interseal battery saver, which prevents initial battery current drain bef ore it is first used. for exam ple, battery-backed rtcs are commonly packaged on a board with a battery connected. in order to preserve batte ry life, the isl12008 will not draw any power from the battery source until after the device is first powered up from the v dd source. thereafter, the device will swit chover to battery backup mode whenever v dd power is lost. the isl12008 has the reseal f unction, which allows the device to enter into the inters eal battery saver mode after manufacture testing for board func tionality. to use the reseal function, simply set reseal bit t o 1 (address 0bh) after the testing is completed. it will e nable the intersea l battery save r mode and prevents battery current drain before it is first used . real time clock operation the real time clock (rtc) uses an external 32.768khz quartz crystal to maintain an accurate internal representation of sub-second, second, minute, hour , day of week, date, month, and year. the rtc has leap-yea r correction, and corrects for months having fewe r than 31 days. the rtc hours is in 24- hour format only. when the is l12008 powers up after the loss of both v dd and v bat , the rtc will not b egin incrementing until at least one byte is writt en to the rtc registers. the su b- second register will increment a fter power up but it will not casue the other rtc registers to incremnent until at least one byte is written to the rtc registers. accuracy of the real time clock the accuracy of the real t ime clock depends on the frequency of the quartz crystal that is used as the time base f or the rtc. since the resonant frequency of a crystal is temperature dependent, the rt c performance will also be dependent upon temperature. the frequency deviation of the crystal is a function o f the turnover temperature of the crysta l from the crystals nominal frequency. for example, a ~20ppm frequency deviation translates into an accura cy of ~1 minute per month. these parameters ar e available from the crystal manufacturer. the isl12008 pr ovides on-chip crystal compensation networks to adjus t load capacitance to tune oscillator frequency from - 97.0695ppm to +206.139ppm. for more detailed information. see application section on page 16. i 2 c serial interface the isl12008 has an i 2 c serial bus interface that provides access to the control and status registers and the user sram. the i 2 c serial interface is compat ible with other industry i 2 c serial bus protocols using a bidirectional data signal (sda) an d a clock signal (scl). oscillator compensation the isl12008 provides the option of timin g correction due to temperature variation of the c rystal oscillator for either manufacturing calibration or a ctive calibration. the total possible compensation is typically -97.0695ppm to +206.139ppm. two compensati on mechanisms that are available are as follows: 1. an analog trimming (atr) r egister that can be used to adjust individual on-chip digital capacitors for oscillator capacitance trimming. the individual digital capacitor is selectable from a range of 4 .5pf to 20.25pf (based upon 32.758khz). this translates to a calculated compensation of approximately -34ppm to + 80ppm (see atr description on page 16). 2. a digital trimming register (dtr) that can be used to adjust the timing counter by -63. 0696ppm to +1 26.139ppm (see dtr description on page 16).
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 9 of 19 sep 26, 2008 also provided is the ability to adjust the crystal capacitance when the isl12008 switches from v dd to battery backup mode. see battery backup mode (v bat ) to normal mode (v dd ) on page 7. register descriptions the battery-backed r egisters are accessible following a slave byte of 1101000x and reads or writes to addresses [00h:1fh]. the defined addresse s and default values are described in table 1. address 12h to 1eh are not used. reads or writes to 12h to 1eh will not affect operation of the device but should b e avoided. register access the contents of address 00h to 07h can be m odified by performing a byte or a page wri te operation directly to any register address. in a page write operation to address 00h to 07h, the address will wrap aro und from 07h to 00h. all the other registers (addre ss 08h to 11h and 1fh) can be modified by performing a byte write operation. the registers are divided into 3 sections. these are: 1. real time clock (8 bytes): address 00h to 06h, and 1fh. address 1fh is sub-second reg ister and it is a read-only. 2. control and status (4 bytes): address 07h to 0bh. 3. alarm (6 bytes): address 0ch to 11h. there are no addr esses above 1fh. address 12h to 1eh ar e not used. reads o r writes to 12h to 1eh will not affect operati on of the devic e but should be avoided. a register can be read by per forming a random read at any address at any time. this returns the contents of that register location. additional register s are read by performing a sequential read. for the rtc an d alarm registers, the read operation latches all clock regi sters into a buffer, so an upda te of the clock does not change the time being read. a sequential read will not result in the output of data from the memory arra y. at the end of a read, the master supplies a stop condition to end the operation and free the b us. after a read, the address remains at the previous addre ss +1 so the user can execute a current address read and continue reading the next register. in a sequential read, the address will warp around at address 07h to 00h; therefore, please use byte read operation to read the registers afte r address 07h.
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 10 of 19 sep 26, 2008 real time clock registers addresses [00h to 06h, and 1fh] rtc registers (sc, mn, hr, dw, dt, mo, yr, ss) these registers depic t bcd representations of the time. as such, sc (seconds, address 00h ) and mn (minutes, address 01h) range from 0 to 59, hr (hou r, address 02h) is in 24-hour mode with a rang e from 0 to 23, dw (day of the week, address 03h) is 1 to 7, dt (dat e, address 04h) is 1 to 31, mo (month, address 05h) is 1 to 12, yr (year, address 06h) is 0 to 99, and ss (sub-seconds/hundredths of seconds, address 1fh) is 0 to 99. the default for all the time keeping bits are set to 0 at power up. bit d7 of sc register contain the crystal enable/disable bit (s t). setting st to 1 will disable the crystal from oscillating and stop the counting in rtc register. when the st bit is set to 1 , it will casue the of bit to se t to 1 due to no crystal oscill ation on the x1 pin. the st bit is se t to 0 on powe r-up for normal operation. bit d7 of mn register contain t he oscillator fail indicator bit (of). this bit is set to a 1 when the x1 pin has no oscillati on. this bit can be reset when the x1 has crystal oscillation and a write to 0. this bit can only be written as 0 and not as a 1. the of bit is set to 1 at pow er-up from a complete power down (v dd and v bat are removed). address 9, bit 7 is also used as the of bit for ds1340 compatibility, and the two of bits are interchangable. bits d6 and d7 of hr register (century/hours register) contain the century enabl e bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the tu rn of the century (depending upon its initi al state). if ceb is set to a '0', cb will not toggle. the dw register provides a day of the week status and uses three bits dw2 to dw0 to represent the seven days of the week. the counter advance s in the cycle 1-2-3-4-5-6-7-1-2- the assignment of a numerical val ue to a specific day of the week is arbitrary an d may be decided by the system software designer. table 1. register memory map addr. section reg name bit reg 7 6 5 4 3 2 1 0 rtc range default 00h rtc sc st sc22 sc21 sc20 sc13 sc12 sc11 sc10 0 to 59 00h 01h mn of mn22 mn21 mn20 mn13 mn12 mn11 mn10 0 to 59 80h 02h hr ceb cb hr21 hr20 hr13 hr12 hr11 hr10 0 to 23 00h 03h dw00000dw12dw11dw101 to 700h 04h dt 0 0 dt21 dt20 dt13 dt12 dt11 dt10 1 to 31 00h 05h mo 0 0 0 mo20 mo13 mo12 mo11 mo10 1 to 12 00h 06h yr yr23 yr22 yr21 yr20 yr13 yr12 yr11 yr10 0 to 99 00h 07h control dtr out ft dtr5 dtr4 dtr3 dtr2 dtr1 dtr0 n/a 80h 08h int0almelpmode00000n/a00h 09h ofof0000000n/a80h 0ah atr bmatr1 bmatr0 atr5 atr4 atr3 atr2 atr1 atr0 n/a 00h 0bh status sr arst xstop reseal 0 0 alm bat rtcf n/a 03h 0ch alarm0 sca esca asc22 asc21 asc20 asc13 asc12 asc11 asc10 00 to 59 00h 0dh mna emna amn22 amn21 amn20 amn13 amn12 amn11 amn10 00 to 59 00h 0eh hra ehra 0 ahr21 ahr20 ahr13 ahr12 ahr11 ahr10 0 to 23 00h 0fh dta edta 0 adt21 adt20 adt13 adt12 adt11 adt10 1 to 31 00h 10h moa emoa 0 0 amo20 amo13 amo12 amo11 amo10 1 to 12 00h 11h dwaedwa0000adw12adw11adw101 to 700h 1fh (read- only) rtc ss ss23 ss22 ss21 ss20 ss13 ss12 ss11 ss10 0 to 99 00h note: 0 = must be set to0
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 11 of 19 sep 26, 2008 leap years leap years add the day february 29 and are defined as those years that are divisible by 4. y ears divisible by 100 are not l eap years, unless they are also divi sible by 400. this means that t he year 2000 is a leap year, the year 2100 is not. the isl12008 do es not correct for the leap year in the year 2100. control and status registers addresses [07h to 0bh] the control and status regist ers consist of the status register, interrupt and alarm register, analog trimming and digital trimming registers. status register (sr) [address 0bh] the status register is located in the memory map at address 0bh. this is a volatile register that provides either control o r status of rtc failure, battery m ode, alarm trigger, crystal oscillator status, reseal? and auto reset of status bits. real time clock fail bit (rtcf) this bit is set to a 1 after a total power failure. this is a read only bit that is set by hardware (isl12008 internally) when the device powers up after having lost all power to the device (bot h v dd and v bat go to 0v). the bit is s et regardless of whether v dd or v bat is applied first. the loss of only one of the supplies does not set the rtcf bi t to 1. on power-up after a total power failure, all register s are set to their default sta tes and the clock will not increment until at least one byte is wri tten to the clock register. the first valid write to the rtc section after a complete power failure resets the rtcf bit to 0 (writing one byte is sufficient). battery bit (bat) this bit is set to a 1 when t he device enters battery backup mode. this bit can be reset either manually by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in t he sr can only set it to 0, not 1. alarm bit (alm) these bits announce if the alarm matches the real time clock. i f there is a match, the respective bit is set to 1. this bit ca n be manually reset to 0 by the user or automatically reset by enabling the auto-reset bit (see arst bit). a write to this bit in the sr can only set it to 0, not 1. note: an alarm bit that is set by an alarm occurring during an s r read operation will remain set after the read operation is complete. reseal (reseal) the reseal? enables the devic e enter into t he interseal? battery saver mode after manufacture testing for board functionality. the factory defaul t setting of this bit is 0. the reseal must be set to 0 to e nable the battery function during normal operation or full functional testing. to use the reseal function, simpl y set reseal bi t to 1 after the testing is completed. it will enable the interseal? battery saver mode and prevents battery current dra in before it is first used. auto reset enable bit (arst) this bit enables/disables the aut omatic reset of the bat, alm and tmr status bits only. when a rst bit is set to 1, these status bits are reset to 0 af ter a valid read of the respecti ve status register (with a valid stop condition). when the arst is cleared to 0, the user mu st manually reset the bat and alm bits. interrupt control register (int) [address 08h] low power mode bit (lpmode) this bit enables/disables low power mode. with lpmode = 0, the device wil l be in normal mode and the v bat supply will be used when v dd < v bat - v bathys and v dd < v trip . with lpmode = 1, t he device will be in low power mode and the v bat supply will be used when v dd < v bat -v bathys . there is a supply current saving of about 600na when using lpmode = 1 with v dd = 5v. (see typical performance curves on page 6: i dd vs v cc with lpmode on and off.) alarm enable bit (alme) this bit enables/disables the a larm function. when the alme bit is set to 1, the al arm function is enabled. when the alme bit is cleared to 0, the alarm function is disabled. alme bit is set to 0 at power-up. oscillator fail register (of) [address 09h] oscillator fail bit (of) this bit is set to a 1 when the x1 pin has no oscillation. th is bit can be reset when the x1 has crystal oscillation and a writ e to 0. this bit can only be wr itten as 0 and not as a 1. t he of bit is set to 1 at power u p from a complete power down (v dd and v bat are removed). address 1, bit 7 is also used as the of bit for m41t00s compatibi lity, and the two of bits are interchangable. table 2. status register (sr) addr 7 6 5 4 3 2 1 0 0bh arst 0 reseal 0 0 alm bat rtcf default 0 0 0 0 0 0 1 1 table 3. interrupt control register (int) addr7 6 5 4 3210 08h 0almelpmode 0 0000 default 0 0 0 0 0 0 0 0 table 4. interrupt control register (int) addr7 6543210 09h of0000000 default1 0000000
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 12 of 19 sep 26, 2008 analog trimming register (atr) [address 0ah] analog trimming register (atr<5:0>) six analog trimming bits, atr0 to atr5 , are provided in order to adjust the on-chip load capa citance value for frequency compensation of the r tc. each bit has a different weight for capacitance adjustment. for e xample, using a citizen cfs- 206 crystal with different atr bit combinations provides an estimated ppm adjustment ran ge from -34ppm to +80ppm to the nominal frequency compens ation. the combination of analog and digital trimming c an give up to -97.0695ppm to +206.139ppm of total adjustment. the effective on-chip se ries load capacitance, c load , ranges from 9pf to 40.5pf with a mid-sca le value of 12.5p f (default). c load is changed via two digitally controlled capacitors, c x1 and c x2 , connected from the x1 and x2 pins to ground (see figure 9). the value of c x1 and c x2 are given in equation 1: the effective series load capacitance is the combination of c x1 and c x2 in equation 2: where b5 is atr5 bit, b4 is at r4 bit, b3 is atr3 bit, b2 is atr1 bit, and b0 is atr0 bit. for example, c load (atr = 000000b [0d]) = 12.5pf, c load (atr = 100000b [32d]) = 4.5pf and c load (atr = 011111b [31d]) = 20.25pf. the entire range for the series combination of load capacitance goes from 4 .5pf to 20.25pf in 0.25pf steps. note that these are typical values. battery mode atr selection (bmatr <1:0>) since the accuracy of the crystal oscillator is dependent on th e v dd /v bat operation, the isl12008 provides the capability to adjust the capaci tance between v dd and v bat when the device switches between power sources. digital trimming register (dtr) [address 07h] digital trimming r egister (dtr<5:0>) six digital trimming bits, dtr0 to dtr5 , are provided to adjust the average number of counts per second and average the ppm error to achieve better accuracy. ? dtr5 is a sign bit. dtr5 = 0 means frequency compensation is < 0. dtr 5 = 1 mean s frequency compensation is > 0. ? dtr<4:0> are scale bits. with dtr5 = 0, dtr<4:0> gives - 2.0345ppm adjustme nt per step. with dtr5 = 1, dtr<4:0> gives +4.0690ppm adjustment per step. a range from -63.0696ppm to +126.139ppm can be represented by using these 3 bits. for example, with dtr = 11111, the digital adjustment is (1111b[15d]*4.0690) = +126.139ppm. with dtr = 01111, the digital adjustment is (-(1111b[15d]*2.0345)) = -63.0696ppm. 512hz frequency ou tput enable bit (ft) this bit enables/disables the 512hz frequency output on the ft/out pin. when the ft is set to 1, the ft/out pin outputs the 512hz frequency, regardless of the digital output selection bit (out). the 512hz frequency output is used for crystal compensation with atr and dtr registers. when the ft is set to 0, the 512hz frequency is d isabled and the function of ft/out pin is selected by the digital output selection bit (out ). the ft bit is set to 0 on power-up. the ft/out pin is an open drain output requires the us e of a pull-up resistor. digital output selection bit (out) this bit selects the output status of the ft/out. 512hz frequency output enable bit (ft) must be set to 0 (disable) for out to take effect on ft/o ut pin. when the out is set to 1 and ft is set to 0, the ft/o ut pin is set to logic level table 5. analog trimming register (atr) addr7 6 543210 0ah bmatr1 bmatr0 atr5 atr4 atr3 atr2 atr1 atr0 default0 0 000000 figure 9. diagram of atr c x1 x1 x2 crystal oscillator c x2 c x 16 b 5 ? 8 b 4 4 b3 2 b2 1 b1 0.5 b0 9 + ? + ? + ? + ? + ? + ?? pf = (eq. 1) c load 1 1 c x1 ---------- - 1 c x2 ---------- - + ?? ?? ---------------------------------- - = c load 16 b5 ? 8 b4 4 b3 2 b2 1 b1 0.5 b 09 + ? + ? + ? + ? + ? + 2 --------------------------------------------------------------- --------------------------------------------------------------- ?? ?? pf = (eq. 2) bmatr1 bmatr0 delta capacitance (c bat to c vdd ) 0 0 0pf 0 1 -0.5pf ( ? +2ppm) 1 0 +0.5pf ( ? -2ppm) 1 1 +1pf ( ? -4ppm) table 6. digital trimming register (dtr) addr 7 6 543210 07h out ft dtr5 dtr4 dtr3 dtr2 dtr1 dtr0 default0 0 000000
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 13 of 19 sep 26, 2008 high. the ft/out pin voltage level is controlled by the voltage of the pull-up resistor on ft/ou t pin. when the out is set to 0 and ft is set to 0, the ft/out pin is set to logic level low. the voltage level of ft/out is set to vol level. the out bit is set to 1 on power-up. the ft/out pin is an open drain output requires the use of a pull-up resistor. alarm registers addresses [0ch to 11h] the alarm register bytes are s et up identical to the rtc register bytes, except that the msb of each byte functions as an enable bit (enable = 1). the se enable bits specify which alarm registers (seconds, minut es, etc.) are used to make the comparison. note that there is no alarm byte for year and sub- second, and the register order f or alarm register is not a 100% matching to the rtc register so please take caution on programming the alarm function. the alarm function wo rks as a comparison between the alarm registers and the rt c registers. as t he rtc advances, the alarm will be triggered once a match occurs between the alarm registers and the rt c registers. any o ne alarm register, multiple registers, or all regis ters can be enabled for a match . to clear an alarm, the alm status bit must be set to 0 with a write. note that if the arst bit is set to 1 (address 0bh, bi t 7), the alm bit will aut omatically be clear ed when the status register is read. i 2 c serial interface the isl12008 supports a bidirecti onal bus oriented protocol. the protocol defines any device that send s data onto the bus as a transmitter and the receivi ng device as the receiver. the device controlling the transfer i s the master and the device being controlled is the slave. th e master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl12008 operates as a slave device in all applications. all communication over the i 2 c bus is conducted by sending the msb of each by te of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 10). on power-up of the isl12008, the sd a pin is in the input mode. all i 2 c bus operations must begin with a star t condition, which is a high to low transit ion of sda while scl is high. the isl12008 contin uously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 10). a start condition is ignored duri ng the power-up sequence. all i 2 c bus operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 10). a stop condition at the end of a read operation or at the end of a w rite operation to memory only places the device in its standby mode. an acknowledge (ack) is a software convention used to indicate a successful data tran sfer. the transmitting device, either master or slave, releases the sda bus after transmitting 8 bits. during the ninth clock cycle, the receiver pulls the sd a line low to acknowledge the rece ption of the 8 bits of data (see figure 11). the isl12008 responds with an ack after recognition of a start condition followed by a v alid identificat ion byte, and once again after succe ssful receipt of an address byte. the isl12008 also responds with an ack after receiving a data byte of a write ope ration. the master must respond with an ack after receiving a data byte of a read operation. figure 10. valid data changes, start, and stop conditions sda scl start data data stop stable change data stable
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 14 of 19 sep 26, 2008 figure 11. acknowledge response from receiver figure 12. byte write sequence sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance s t a r t s t o p identification byte data byte a c k signals from the master signals from the isl12008 a c k 10 0 11 a c k write signal at sda 000 address byte
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 15 of 19 sep 26, 2008 device addressing following a start condition, the master must output a slave address byte. the 7 msbs are t he device identifiers. these bits are 1101000. the last bit of the slave addre ss byte defines a read or write operation to be performed. when this r/w bit is a 1, then a read operation is selected (re fer to figure 16). when this r/w bit is a 0 , then a write operation (refer to figure 12). after loading the entire slave address byte from the sda bus, the isl12008 compares the slave bit and device select bits with 1101000. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up, the internal address counter is set to address 0h, so a current address read of the ccr array starts at address 0h. when required, as part of a random read, the ma ster must supply t he 1 word address bytes, as shown in figure 14. in a random read oper ation, the slave byte in the dummy write portion must m atch the slave byte i n the read section. for a random read of the clock/control re gisters, the slave byte must be 1101000x in both places. write operation a write operation requires a s tart condition, followed by a valid identification byte, a valid address byte, a data byte, a nd a stop condition. after each of the three by tes, the isl12008 responds with an ack. after re ceived the stop condition, the isl12008 writes the data into the memory, then the i 2 c bus enters a standby state. after a write operation, the internal address pointer will remain at the address for the last data by te written. read operation a read operation consists of a t hree byte instru ction followed by one or more data bytes (s ee figure 14). the master initiates the operation issuing the following sequence: a start, the identificatio n byte with the r/w bit set to 0, an address byte, a second start , and a second i dentification byte with the r/w bit set to 1. after each of the three bytes, the isl12008 respon ds with an ack. then the isl12008 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop condition) following the last bit of the last data byte (see fi gure 14). the data bytes are from the memo ry location indicated by an internal address pointer. this internal address pointer initial value is determined by the address byte in the read operation instruction, and increments by one during transmission of each data byte. figure 13. slave address, word address, and data bytes slave address byte d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte a6 a5 1 10 0 1 0 r/w 0 word address figure 14. read sequence signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 0 s t o p a c k 1 identification byte with r/w = 1 a c k s t a r t last read data byte first read data byte a c k 10 1 1000 10 1 10 00
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 16 of 19 sep 26, 2008 application section oscillator crys tal requirements the isl12008 uses a standard 32.768khz crystal. either through hole or surface mount cr ystals can be used. table 7 lists some recommended surface mount crystals and the parameters of each. this lis t is not exhaustive and other surface mount devices can be u sed with the is l12008 if their specifications are very simila r to the devices listed. the crystal should have a required parallel load capacitance of 12.5pf and an equivalent serie s resistance of less than 50k. the crystals temperature range specification should match the application. many crystals are rated for -10c to +60c (especially through-hole and t uning fork types), so an appropriate crystal should be selected if extended temperature range is required. crystal oscillator frequency adjustment the isl12008 device contains c ircuitry for adjusting the frequency of the crystal oscillat or. this circuitry can be used to trim oscillator initial accuracy as well as adjust the frequenc y to compensate for tem perature changes. the analog trimming register (atr) is used to adjust the load capacitance seen by the crystal. there are 6 bits of atr contro l, with linear capacitance increments available for adjustment. since the atr adjustment is es sentially pulling the frequency of the oscillator, the resultin g frequency changes will not be linear with incremental capac itance changes. the equations (which govern pulling) show that l ower capacitor values of atr adjustment will provide larger increments. also, the higher values of atr adjustment will produce smaller incremental frequency changes. the range aff orded by the atr adjustment with a typical surface mount c rystal is typically -34ppm to +80ppm around the atr = 0 de fault setting because of this property. the user should note this when using the atr for calibration. the temperature dr ift of the capacitance used in t he atr control is extremely low, so this feature can be used for temperature compensation with good accuracy. in addition to the analog c ompensation afforded by the adjustable load capacitance, a dig ital compensation feature is available for the is l12008. there are 6 b its known as the digital trimming register ( dtr). the range provided is -63.0695ppm to +126.139ppm. dtr operates by adding or skipping pulses in the clock count er. it is very useful for coa rse adjustments of frequency drift over temperature or extending the adjustment range avail able with the atr register. initial accuracy is best adjusted by enabling the 512hz frequency output (using the ft bit, address 08h bit 6), and monitoring the ft/out pin with a calibrated frequency counter. the gating time should be set long enough to ensure accuracy to at least 1ppm. to calcula te the ppm on the measured 512hz, simply divide the m easured 512hz by 512, then subtract 1 from the result and mulitple by 1,000,000. please see equation 3 for the formula: the atr should be se t to the center posit ion, or 00000b, to begin with. once the initial measurement is made, then the atr register can be changed to a djust the frequency. note for a range of 0 to 31 for the atr register will increased capacitance and lower the freq uency with 31 for the maximum negative correction, and for a range of 32 to 63 for the atr register will decreased capacitance and increase the frequency with 32 for the maximum positiv e correction. i f the initial measurement shows the frequ ency is far off, it will be necessary to use the dtr regist er to do a coarse adjustment. note that most all crystals w ill have tight enough initial accuracy at room temperature so that a small atr register adjustment should be all that is needed. temperature compensation the atr and dtr controls can be combined to provide crystal drift temperature compensation. the typical 32.768khz crystal has a drift characteristic that i s similar to that shown in fig ure 15. there is a turnover temperature (t 0 ) where the drift is very near zero. the shape is parabolic as it varies with the square of the difference between t he actual temperature and the turnover temperature. if full industrial temperature co mpensation is desired in an isl12008 circuit, then both th e dtr and atr registers will table 7. suggested surface mount crystals manufacturer part number citizen cm200s epson mc-405, mc-406 raltron rsm-200s saronix 32s12 ecliptek ecpsm29t-32.768k ecs ecx-306 fox fsm-327 ppm = (ft/512 - 1)*1e6 (eq. 3) temperature (c) -160 -140 -120 -100 -80 -60 -40 -20 0 -40-30-20-100 1020304050607080 ppm figure 15. rtc crystal temperature drift
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 17 of 19 sep 26, 2008 need to be utilized (total corre ction range = -97.0695ppm to +206.139ppm). a system to implem ent temperature compensation would consist of the isl12008, a t emperature sensor, and a microcontroller. these devices may already be in the system so the function will just be a mat ter of implementing software and performing some calculations. fairly accurate temperature compensation can be implemented just by using the crystal manufacturers specifications f or the turnover temperature t 0 and the drift coefficient ( ? ). the formula for calculating the oscillator adjustment necessary is equation 4: once the temperature curve for a crystal is established, then the designer should dec ide at what discrete temperatures the compensation will change. since drift is higher at extreme temperatures, the compensatio n may not be n eeded until the temperature is great er than +20c from t 0 . a sample curve of the atr se tting vs frequency adjustment for the isl12008 and a typica l rtc crystal is given in figure 16. this curve ma y vary with differen t crystals, so it is good practice to evaluate a given crystal in an isl12008 circui t before establishing the adjustment values. this curve is then used to fig ure what atr and dtr settings are used for compensation. the r esults would be placed in a lookup table for the mi crocontroller to access. layout considerations the crystal input at x1 has a very high impedance, and oscillator circuits operati ng at low frequencies (such as 32.768khz) are known to pick up noise very easily if layout precautions are not followed. most instances of erratic clockin g or large accuracy errors can be t raced to the susceptibility of the oscillator circuit to interfe rence from adjacent high speed clock or data lines. careful la yout of the rtc circuit will avo id noise pickup and insure accurate clocking. figure 17 shows a s uggested layout for the isl12008 device using a surface mount crystal. two main precautions should be followed: 1. do not run the serial bus lines or any high speed logic lines in the vicinity of the crystal. these logic level lines can induce noise in the oscillator ci rcuit to cause misclocking. 2. add a ground trace aroun d the crystal with one end terminated at the chip ground. this will provide termination for emitted noise in the vi cinity of the rtc device. in addition, it is a good idea t o avoid a ground plane under th e x1 and x2 pins and the crystal, as this will affect the load capacitance and therefore the oscillator accuracy of the circui t. if the ft/out pin is used as a c lock, it should be routed away from the rtc device as well. the traces for the v bat and v cc pins can be treated as a gr ound, and should be routed around the crystal. super capacitor backup the isl12008 device provides a vbat pin which is used for a battery backup input. a super c apacitor can be used as an alternative to a battery in ca ses where shorte r backup times are required. since the battery b ackup supply current required by the isl12008 is extremely low , it is possible to get months of backup operation us ing a super capacitor. typical capacitor values are a few f to 1f or more, depending on the application. if backup is only needed for a few minutes, then a small inexpensive electrolytic capaci tor can be used. for extended periods, a low leakage, high ca pacity super capacitor is the best choice. these devices are available from such vendors as panasonic and murata. the main specifications include working voltage and leakage curr ent. if the application is for charging the capacitor from a +5v 5% supply with a signal diode, then the voltage on the capacitor can vary from ~4.5v to slightly over 5.0v. a capacito r with a rated wv of 5.0v may have a reduced lifetime if the supply voltage is slightly high. the leakage current should be as small as possible. for example, a super capacitor shou ld be specified with leakage of well below 1a. a standard el ectrolytic cap acitor with dc leakage current in the micr oamps will have a severely shortened backup time. following are some examples with equations to assist with calculating backup times and required capacitance for the isl12008 device. the backup suppl y current plays a major part in these equations, and a ty pical value was chosen for example purposes. for a robus t design, a margin of 30% should be included to cover s upply current and capacitance tolerances over the results o f the calculations. even more adjustment(ppm) t t 0 C ?? 2 = ? ? (eq. 4) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 50 55 60 atr setting ppm adjustment figure 16. atr setting vs oscillator frequency adjustment figure 17. suggested layout for isl12008 and crystal
isl12008 i 2 c real time clock wit h battery backup fn6690 rev 1.00 page 18 of 19 sep 26, 2008 margin should be included if periods of very warm temperature operation are expected. example 1: calculating backup time given voltages and capacitor value in figure 18, use c bat = 0.47f and v cc = 5v. with v cc = 5v, the voltage at v bat will approach 4.7v as the diode turns off completely. the isl12008 is specified to operate down to v bat = 1.8v. the capacitance charge/di scharge in equation 5 is used to estimate the total backup time as follows: rearranging gives equation 6: c bat is the backup capacitanc e and dv is t he change in voltage from fully charged to loss of operation. note that i tot is the total of the supply current of the isl12008 (i bat ) plus the leakage current of the ca pacitor and the diode, i lkg . in these calculations, i lkg is assumed to be extremely small and will be ignored. if an application requi res extended operation at temperatures over +5 0c, these leakages will increase and hence reduce backup time. note that i bat changes with v bat almost linearly (see typical performance curves on page 6) . this allows us to make an approximation of i bat , using a value midway between the two endpoints. the typical linear equation for i bat vs v bat is shown in equation 7: using equation 7 to solve for the average current given 2 voltage points gives equation 8: combining with equation 6 gives the equation for backup time in equation 9: where: c bat = 0.47f v bat2 = 4.7v v bat1 = 1.8v i lkg = 0 (assumed minimal) solving equation 8 f or this example (i batavg = 4.387e-7a) yields equation 10: since there are 86,400 seconds in a day, this corresponds to 35.96 days. if the 30% tolerance is included for capacitor and supply current tolerances, then worst case backup time would be represented in equation 11: example 2: calculating a capacitor value for a given backup time referring to figure 18 again, the capacitor value needs to be calculated to give 2 months ( 60 days) of backup time, given v cc = 5.0v. as in example 1, the v bat voltage will vary from 4.7v down to 1.8v. we will need to rearrange equation 6 to solve for capacitance in equation 12: using the terms previously described, equation 12 becomes equation 13: where: t backup = 60 days*86,400 sec/day = 5.18 e6 seconds i batavg = 4.387 e-7a (same as example 1) i lkg = 0 (assumed) v bat2 = 4.7v v bat1 = 1.8vsolving gives c bat = 5.18 e6*(4.387 e-7)/(2.9) = 0.784f if the 30% tolerance is included for tolerances, then worst cas e capacitor value would be: figure 18. supercapacitor charging circuit 2.7v to 5.5v v cc v bat gnd 1n4148 c bat i = c bat dv/dt (eq. 5) dt = c bat dv/i tot to solve for bacup time. (eq. 6) i bat = 1.031e-7(v bat ) + 1.036e-7a (eq. 7) i batavg = 5.155e-8(v bat2 + v bat1 ) + 1.036e-7a (eq. 8) t backup = c bat (v bat2 - v bat1 ) / (i batavg + i lkg ) (eq. 9) seconds (eq. 10) t backup 0.47 2.9 ?? 4.38e 7 3.107e6s = C ? ? = = ? days = = = + C = ? =
fn6690 rev 1.00 page 19 of 19 sep 26, 2008 isl12008 i 2 c real time clock wit h battery backup intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2008. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 ? 0 8 0 8 - rev. 1 6/05

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